This application claims priority to Italian Patent Application Serial No. RM2001A000524, filed Aug. 30, 2001, entitled xe2x80x9cFLASH MEMORY ARRAY STRUCTURE.xe2x80x9d
The present invention relates generally to non-volatile memory devices and in particular the present invention relates to a flash memory array structure having independently operating memory arrays.
A flash memory is a type of non-volatile memory. That is, a flash memory is a type of memory that retains stored data without a periodic refresh of electricity. An important feature of a flash memory is that it can be erased in blocks instead of one byte at a time. Each erasable block of memory comprises a plurality of non-volatile memory cells (cells) arranged in rows and columns. Each cell is coupled to a word line, bit line and source line. In particular, a word line is coupled to a control gate of each cell in a row, a bit line is coupled to a drain of each cell in a column and the source line is coupled to a source of each cell in an erasable block. The cells are programmed and erased by manipulating the voltages on the word lines, bit lines and source lines.
Recently, flash memory devices have been designed with two independent banks of memory cells. This design allows for concurrent memory operations such as read-while write or read-while-erase. For example, while one processor writes to one location of a bank, a second processor can read a memory location in another bank. This design has particular application in cellular phone systems. In a cellular phone application, a first bank can be used to store a code for operation of the phone and the second bank can be used to store data. In a typical cellular phone application, a first bank takes approximately 75% of the total memory and the second bank takes approximately 25% of the total memory. However, for different cellular phones and different applications different partition percentages may be desired. To achieve desired partition percentages, a manufacture must design separate devices for each application. An efficient way to design and manufacture a device that can fulfill a large number of applications is needed.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for a flash memory design that allows for an easy and efficient way to provide partition percentages of memory banks.
The above-mentioned problems with memory devices and other problems are addressed by the present invention and will be understood by reading and studying the following specification.
In one embodiment, a flash memory device is disclosed. The flash memory device comprises a poly silicon layer, a first metal layer and a second metal layer. The poly silicon layer has a plurality of word lines formed therein. The word lines are coupled to rows of memory cells. The first metal layer has a plurality of local bit lines formed therein. The local bit lines are coupled to columns of memory cells. The second metal layer has a plurality of global bit lines formed therein. The global bit lines are selectively coupled to the plurality of local bit lines. The global bit lines are further selectively bisected during manufacture to form a first bank and a second bank of memory cells. The first and second banks allow concurrent memory operations to be performed on the flash memory device.
In another embodiment, a non-volatile memory device comprises a first and second bank, word lines, local bit lines and global bit lines. Each bank has a pair of quadrants of non-volatile memory cells. The memory cells in each quadrant are arranged in row and column fashion. There is a word line for each row of memory cells in each quadrant. Each word line is formed in a poly silicon layer. There is a local bit line for each column in each quadrant. Each local bit line is formed in a first metal layer. A plurality of the global bit lines are selectively coupled to the local bit lines in each quadrant. The global bit lines are formed in a second metal layer. Moreover, the global bit lines are disconnected at selected locations to form the first and second bank.
In another embodiment, a flash memory device comprises a memory array, word lines, local bit lines and global bit lines. The memory array has memory cells arranged in rows and columns. There is a word line for each row of memory cells in the memory array. Each word line is formed in a poly silicon layer. There is a local bit line for each row of memory cells in the memory array. Each local bit line is formed in a first metal layer. A plurality of the global bit lines are selectively coupled to the local bit lines. Each global bit line is formed in a second metal layer. The global bit lines are selectively bisected to form a first and second bank of memory cells in the memory array to allow concurrent memory operations.
A method of forming a flash memory device having a pair of independently operating memory arrays comprising, bisecting global bit lines at predetermined locations during manufacture of the flash memory device to form independently operating memory arrays.
A method of forming a flash memory device comprising, forming word lines in a poly silicon layer, forming local bit lines in a first metal layer, forming global bit lines in a second metal layer, wherein the first metal layer is positioned between the poly silicon layer and the second metal layer and masking the second metal layer while the global bit lines are being formed to break the global bit lines at desired locations, wherein a first and second bank of memory cells in the flash memory device is formed.
Another method of forming a flash memory device comprising, forming word lines in a poly silicon layer, wherein the word lines are coupled to gates of memory cells arranged in columns in a memory array, forming local bit lines in a first metal layer, wherein the local bit lines are coupled to drains of memory cells arranged in rows in the memory array, forming global bit lines in a second metal layer, wherein the global bit lines are selectively coupled to the local bit lines and bisecting the global bit lines at predetermined locations to form a first and second bank in the memory array, wherein concurrent memory operations can be performed on the first and second banks.